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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:25:51 09/24/2013 
-- Design Name: 
-- Module Name:    xor_and_or_32 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xor_and_or_32 is
    Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
           b : in  STD_LOGIC_VECTOR (31 downto 0);
           andOutput : out  STD_LOGIC_VECTOR (31 downto 0);
           orOutput : out  STD_LOGIC_VECTOR (31 downto 0);
           xorOutput : out  STD_LOGIC_VECTOR (31 downto 0));
end xor_and_or_32;

architecture Behavioral of xor_and_or_32 is
begin
	
	orOutput <= a or b;
	andOutput <= a and b;
	xorOutput <= a xor b;

end Behavioral;

